1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a fabricating method and a high-voltage device.
2. Description of the Related Art
A high voltage device is one of the most important devices utilized in highly integrated circuits. Erasable programmable read only memory (EPROM) and flash memory are two of the high-voltage devices most often used in computers and electronic products. In general, operating a device under high voltage can increase the speed of a read or a write operation. Thus, high-voltage devices, which can be operated under high voltage, are required in integrated circuit.
Due to the increasing number of semiconductor devices incorporated in integrated circuits, the size of transistors needs to be decreased. Accordingly, as the channel length of the transistors is decreased, the operating speed is increased. However, there is an increased likelihood of a problem, referred to as a "short channel effect", caused by the reduced channel length. If the voltage level is fixed, according to the equation of electrical field=electrical voltage/channel length, as the channel length is shortened, the strength of the electrical field is increased. Thus, as the strength the of electrical field increases, the energy of the electron increases and electrical breakdown is likely to occur.
In a conventional high-voltage device, occurrence of potential crowding on the edge of the drain region decreases breakdown voltage. In order to increase the breakdown voltage and make the device operable under high voltage, the doping concentration of the drift region must be decreased. Unfortunately, as the doping concentration of the drift region decreases, the current driving performance decreases.
In the conventional high-voltage device, the formation of an isolation layer is used for the purpose of increasing the channel length. In addition, a lightly doped ion implantation is performed on the junction between a depletion region and a source/drain region in order to decrease the hot electron effect. In this way, the breakdown voltage of the source/drain region increases. The high-voltage device is able to work normally under a high electrical voltage.
FIG. 1 is a schematic, cross-sectional view showing a portion of a conventional high-voltage device.
In FIG. 1, two field oxide layers 102 are formed in the P-type silicon substrate 100. A gate oxide layer 112 is formed on the substrate 100 between the two field oxide layers 102. The field oxide layers 102 are used to increase the channel length between an N.sup.+ -type source region 106 and an N.sup.30 -type drain region 108. An N.sup.- -type lightly doped region 116 is to the side of one of the field oxide layers 102. An N.sup.- -type lightly doped region 118 is to the side of the other of the field oxide layers 102. A portion of a gate 104 is on the gate oxide layer 112 and the other portion of the gate 104 is on the field oxide layers 102. The N.sup.- -type lightly doped regions 116 and 118 are used as drift regions for carriers while the device is operated. As a junction depth of the N.sup.- -type lightly doped regions 116 and 118 increases, the effective channel length decreases. Moreover, the N.sup.- -type lightly doped regions 116 and 118 are not easily formed in a precise location in the conventional method. There are also P-N junctions (not shown) formed between the N.sup.- -type lightly doped region 116 and the substrate 100 or between the N.sup.- -type lightly doped region 118 and the substrate 100. The P-N junction regions are called depletion regions. The electrical distribution lines, which are nearby the channel, of the N.sup.+ -type lightly doped drain region 108 have higher curvature while the device is operated under high voltage. The breakdown voltage thus is decreased. Consequently, the device cannot work normally under high-voltage.